Testing is an indispensable step in integrated memory manufhewre. Standard tests involve writing data to a memory cell and subsequently reading the memory cell to detect whether the memory cell has retained the data. Normal writing and reading allows the detection of a number of circuit errors in the memory cell, but not all. Additional measures are needed to detect other errors.
U.S. Pat. No. 5,835,429 describes a method of testing for weak SRAM memory cells that are unable to retain data permanently, U.S. Pat. No. 5,559,745 discloses a similar test technique. The cells are tested by writing data with lowered word line voltage. The word line voltage controls the conductivity of access transistors that connect the memory cell to the bit lines. By lowering the word line voltage the access transistors are made less conductive during writing. As a result data is written only weakly into the cell. This is sufficient to write into weak memory cells, but insufficient to write into normal, xe2x80x9cstrongxe2x80x9d memory cells. Hence, weak cells show up when data is read from the cells after weak writing.
U.S. Pat. No. 5,930,185 also discloses lowering the word line voltage during writing for test purposes, but in this case defective cells are distinguished from normal cells because the defective cells do not retain the weakly written data.
Newly developed integrated circuit manufacturing processes continuously reduce the dimensions of transistors used in SRAM memory cells. As a result, discrepancies between the parameters of different transistors in the memory cell become relatively more important. It has been found that if the discrepancy is too large, the noise margin of the memory cell is reduced to an unacceptably low level. This is hard to test, because it would take a very long time to determine how all cells in a very large memory respond to noise.
Amongst others, it is an object of the invention to test the noise margin of static memory cells.
The method of testing SRAM memory cells according to the invention is set forth in claim 1. According to the invention, data is written into an SRAM memory cell and read back. In between, the ratio between the conductivity of the access transistors and the drive strength of the inverters in the static memory cells is made higher than during the normal mode, for example by applying a voltage outside the power supply range to the word line of the memory cell, so as to make the access transistors more conductive than during normal use, while applying substantially equal voltages to the bit lines.
Thus, the access transistors and the bit lines operate to provide a relatively higher load to the memory cell than in the normal mode. This shifts the voltages in the memory cell, mimicking the result of noise. If the cell has sufficient noise margin, it will return to its original state once the voltage on the wordline is returned to normal. If, not, the state of the memory cell will flip, which is detected by reading the content of the cell. To support such a test, an SRAM device according to the invention contains means for applying a voltage to the wordline outside its normal range in the test mode, while applying substantially equal voltages to the bit lines.